Minimum Energy Sub-Threshold Self-Timed Circuits Using Current Sensing Completion Detection

This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). To support this, a fully-decoupled latch controller has been developed, which integrates with the current sensing circuitry. Different configurations in which the latch controller can be used are highlighted. The paper also outlines a corresponding design flow briefly, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. Different use cases for the CSCD system are examined. The design flow and the current-sensing technique is validated by the implementation of a self-timed version of a wavelet based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip has been fabricated and verified to operate down to 250 mV. The improvement in throughput due to asynchronous operation is 52.58 %. By trading the throughput improvement, energy dissipation is reduced by 16.8 % at the energy-minimum supply voltage.